1. Field of the Invention
The invention relates to a method for fabricating semiconductor devices and in particular fin field-effect transistors.
2. Background of the Invention
Fin field-effect transistors (also called FinFets hereinafter) are a well known alternative to planar or vertical field-effect transistor structures for applications which require field-effect transistors having channel lengths (device length) of less than 100 nm.
FIG. 1 illustrates a fin field-effect transistor 100 in simplified fashion. A fin 102 made of a semiconductor material is formed on a substrate 104. Fin 102 is encapsulated by a gate electrode structure 106 from three sides in a section 108. A gate dielectric (not illustrated in the figure) is arranged between the gate electrode structure 106 and fin 102 at least in the section 108. The section 108 of fin 102 is adjoined by source/drain regions S/D, S/D′ on both sides. In the example illustrated, the source/drain regions 110, 110′ expand at both head ends of fin 102 in order to facilitate a contact connection of the source/drain regions. In addition, even further FinFet structures are known which differ in the formation of the source/drain regions and of the fin. It is also known, for example, that a plurality of fins can be formed parallel to one another between two corresponding source/drain regions of a fin field-effect transistor.
A characterizing feature of fin field-effect transistors is that even at a low gate voltage, majority carriers are removed to a high degree from a channel region (also called active region hereinafter) in which a conductive channel forms in the activated state of the fin field-effect transistor. A parasitic flow of charge carriers to or from the source/drain regions and thus a leakage current via the active region are thus reduced in the nonactivated state of the fin field-effect transistor. Disadvantageous short channel effects known from conventional planar and vertical field-effect transistor structures occur to a lesser extent.
A particular disadvantage about known concepts for fabricating fin flied-effect transistors is that, relative to channel length, the fin field-effect transistors can only be arranged in a relatively low packing density compared with conventional planar or vertical field-effect transistor structures. This is disadvantageous, in particular, in an application of the fin field-effect transistors as selection transistors of capacitive memory cells.